# FPGA

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- A survey of CORDIC algorithms for FPGA based computers R Andraka. 1998. Proceedings of the 1998 ACM/SIGDA sixth …
- VPR: A new packing, placement and routing tool for FPGA research V Betz, J Rose. 1997. International Workshop on Field Programmable Logic …
- FPGA intrinsic PUFs and their use for IP protection J Guajardo, SS Kumar, GJ Schrijen, P Tuyls. 2007. International workshop on …
- FPGA design methodology for industrial control systems—A review E Monmasson, MN Cirstea. 2007. IEEE transactions on industrial …
- Optimizing fpga-based accelerator design for deep convolutional neural networks C Zhang, P Li, G Sun, Y Guan, B Xiao…. 2015. Proceedings of the 2015 …
- A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation K Tiri, I Verbauwhede. 2004. … Design, Automation and Test in Europe …
- FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs J Cong, Y Ding. 1994. … Transactions on Computer-Aided Design of …
- The effect of LUT and cluster size on deep-submicron FPGA performance and density E Ahmed, J Rose. 2004. IEEE Transactions on Very Large Scale …
- Reconfigurable computing: the theory and practice of FPGA-based computation S Hauck, A DeHon. 2010. Journal of Economic Perspectives
- The butterfly PUF protecting IP on every FPGA SS Kumar, J Guajardo, R Maes…. 2008. … Security and Trust
- A time-multiplexed FPGA S Trimberger, D Carberry, A Johnson…. 1997. Proceedings. The 5th …
- FPGA architecture: Survey and challenges I Kuon, R Tessier, J Rose. 2008. Foundations and Trends® in …
- CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices DB Strukov, KK Likharev. 2005. Nanotechnology
- Going deeper with embedded fpga platform for convolutional neural network J Qiu, J Wang, S Yao, K Guo, B Li, E Zhou…. 2016. Proceedings of the …
- LegUp: high-level synthesis for FPGA-based processor/accelerator systems A Canis, J Choi, M Aldham, V Zhang…. 2011. Proceedings of the 19th …
- Dynamic power consumption in Virtex™-II FPGA family L Shang, AS Kaviani, K Bathala. 2002. Proceedings of the 2002 ACM/SIGDA …
- FPGA and CPLD architectures: A tutorial S Brown, J Rose. 1996. IEEE design & test of computers
- OneChip: an FPGA processor with reconfigurable logic. RD Wittig, P Chow. 1997. International journal of epidemiology
- FPGA-based processor J Cloutier. 1999. US Patent 5,892,962
- Advanced FPGA design: architecture, implementation, and optimization S Kilts. 2007. Science
- FPGA implementations of neural networks AR Omondi, JC Rajapakse. 2006. Journal of personality and social psychology
- FPGA repeatable interconnect structure with hierarchical interconnect lines SP Young, K Chaudhary, TJ Bauer. 1999. US Patent 5,914,616
- Very compact FPGA implementation of the AES algorithm P Chodowiec, K Gaj. 2003. International Workshop on Cryptographic Hardware …
- High performance self modifying on-the-fly alterable logic FPGA, architecture and method M Chatter. 1998. US Patent 5,838,165
- FPGA in the software radio M Cummings, S Haruyama. 1999. IEEE communications Magazine
- FPGA-based system design W Wolf. 2004. The sciences
- Stream-oriented FPGA computing in the Streams-C high level language M Gokhale, J Stone, J Arnold…. 2000. Proceedings 2000 IEEE …
- FPGA design and implementation of a real-time stereo vision system S Jin, J Cho, X Dai Pham, KM Lee…. 2009. IEEE transactions on …
- FPGA realization of space-vector PWM control IC for three-phase PWM inverters YY Tzou, HJ Hsu. 1997. IEEE Transactions on power electronics
- Performance benefits of monolithically stacked 3-D FPGA M Lin, A El Gamal, YC Lu…. 2007. IEEE Transactions on …
- Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density A Marquardt, V Betz, J Rose. 1999. FPGA
- A 21.54 Gbits/s fully pipelined AES processor on FPGA A Hodjat, I Verbauwhede. 2004. 12th Annual IEEE Symposium on …
- An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists AJ Elbirt, W Yip, B Chetwynd…. 2001. IEEE Transactions on Very …
- Cnp: An fpga-based processor for convolutional networks C Farabet, C Poulet, JY Han…. 2009. … Conference on Field …
- FPGA prototyping by VHDL examples: Xilinx Spartan-3 version PP Chu. 2011. Journal of monetary Economics
- Efficient packet classification for network intrusion detection using FPGA H Song, JW Lockwood. 2005. Proceedings of the 2005 ACM/SIGDA 13th …
- FPGA configurable logic block with multi-purpose logic/memory circuit RD Wittig, S Mohan, RA Carberry. 2000. US Patent 6,150,838
- VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling J Luu, I Kuon, P Jamieson, T Campbell, A Ye…. 2011. ACM Transactions on …
- Quantitative analysis of floating point arithmetic on FPGA based custom computing machines N Shirazi, A Walters, P Athanas. 1995. … IEEE Symposium on FPGAs …
- Practical FPGA programming in C D Pellerin, S Thibault. 2005. Oecologia
- FPGA implementations of neural networks–a survey of a decade of progress J Zhu, P Sutton. 2003. International Conference on Field Programmable Logic …
- Directional and single-driver wires in FPGA interconnect G Lemieux, E Lee, M Tom, A Yu. 2004. Proceedings. 2004 IEEE …
- Throughput-optimized OpenCL-based FPGA accelerator for large-scale convolutional neural networks N Suda, V Chandra, G Dasika, A Mohanty…. 2016. Proceedings of the …
- A hybrid ASIC and FPGA architecture PS Zuchowski, CB Reynolds, RJ Grupp…. 2002. … on Computer Aided …
- Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM BJ New, RA Johnson, R Wittig, S Mohan. 2000. US Patent 6,091,263
- FPGA architecture with repeatable tiles including routing matrices and logic matrices D Tavana, WK Yee, VA Holen. 1997. US Patent 5,682,107
- The design and implementation of a context switching FPGA SM Scalera, JR Vázquez. 1998. Proceedings. IEEE Symposium on …
- AES on FPGA from the fastest to the smallest T Good, M Benaissa. 2005. … on cryptographic hardware and embedded systems
- FPGA-based current controllers for AC machine drives—A review MW Naouar, E Monmasson…. 2007. IEEE Transactions …
- Performance comparison of FPGA, GPU and CPU in image processing S Asano, T Maruyama…. 2009. … conference on field …
- FPGA-based implementation of signal processing systems R Woods, J McAllister, G Lightbody, Y Yi. 2008. Journal of anatomy
- On area/depth trade-off in LUT-based FPGA technology mapping J Cong, Y Ding. 1994. IEEE Transactions on Very Large Scale …
- 64-bit floating-point FPGA matrix multiplication Y Dou, S Vassiliadis, GK Kuzmanov…. 2005. Proceedings of the 2005 …
- Physical unclonable functions and public-key crypto for FPGA IP protection J Guajardo, SS Kumar, GJ Schrijen…. 2007. … Conference on Field …
- FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in response to those instructions SM Casselman. 1997. US Patent 5,684,980
- An FPGA-Based Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists AJ Elbirt, W Yip, B Chetwynd…. 2000. Proc. Third Advanced …
- Contactless energy transfer system with FPGA-controlled resonant converter AJ Moradewicz…. 2010. IEEE Transactions on …
- A digital architecture for support vector machines: theory, algorithm, and FPGA implementation D Anguita, A Boni, S Ridella. 2003. IEEE Transactions on neural …
- A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH HKH So, R Brodersen. 2008. ACM Transactions on Embedded Computing …
- Hardware implementation of a real-time neural network controller with a DSP and an FPGA for nonlinear systems S Jung, S su Kim. 2007. IEEE Transactions on Industrial Electronics
- FPGA realization of FIR filters by efficient and flexible systolization using distributed arithmetic PK Meher, S Chandrasekaran…. 2008. IEEE transactions on …
- Dynamic hardware plugins in an FPGA with partial run-time reconfiguration EL Horta, JW Lockwood, DE Taylor…. 2002. Proceedings of the 39th …
- Fast, large-scale string match for a 10Gbps FPGA-based network intrusion detection system I Sourdis, D Pnevmatikatos. 2003. International Conference on Field …
- An FPGA-based novel digital PWM control scheme for BLDC motor drives A Sathyan, N Milivojevic, YJ Lee…. 2009. IEEE transactions on …
- FPGA-based speed control IC for PMSM drive with adaptive fuzzy control YS Kung, MH Tsai. 2007. IEEE Transactions on Power Electronics
- NAPA C: Compiling for a hybrid RISC/FPGA architecture MB Gokhale, JM Stone. 1998. Proceedings. IEEE Symposium on …
- Intelligent data storage and processing using fpga devices R Chamberlain, B Brink, J White…. 2007. US Patent App. 10 …
- High performance single-chip FPGA Rijndael algorithm implementations M McLoone, JV McCanny. 2001. International Workshop on Cryptographic …
- FPGA architecture having RAM blocks with programmable word length and width and dedicated address and data lines SP Young. 1999. US Patent 5,933,023
- Large-scale MIMO detection for 3GPP LTE: Algorithms and FPGA implementations M Wu, B Yin, G Wang, C Dick…. 2014. IEEE Journal of …
- A survey and evaluation of FPGA high-level synthesis tools R Nane, VM Sima, C Pilato, J Choi…. 2015. … on Computer-Aided …
- Automatic online diagnosis algorithm for broken-bar detection on induction motors based on discrete wavelet transform for FPGA implementation A Ordaz-Moreno…. 2008. IEEE Transactions …
- FPGA-based real-time optical-flow system J Díaz, E Ros, F Pelayo, EM Ortigosa…. 2006. IEEE transactions on …
- Programmable switch for FPGA input/output signals TA Kean. 1998. US Patent 5,705,938
- Low overhead fault-tolerant FPGA systems J Lach, WH Mangione-Smith…. 1998. IEEE Transactions on …
- Ese: Efficient speech recognition engine with sparse lstm on fpga S Han, J Kang, H Mao, Y Hu, X Li, Y Li, D Xie…. 2017. Proceedings of the …
- Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications G Rouvroy, FX Standaert…. 2004. … and Computing, 2004 …
- Placement and routing tools for the Triptych FPGA C Ebeling, L McMurchie, SA Hauck…. 1995. IEEE Transactions on …
- LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems A Canis, J Choi, M Aldham, V Zhang…. 2013. ACM Transactions on …
- FPGA with parallel and serial user interfaces TA Kean, WA Wilkie. 1998. US Patent 5,737,235
- Virtual wires: Overcoming pin limitations in FPGA-based logic emulators J Babb, R Tessier, A Agarwal. 1993. [1993] Proceedings IEEE …
- A CAD suite for high-performance FPGA design B Hutchings, P Bellows, J Hawkins…. 1999. … IEEE Symposium on …
- Implementation of human-like driving skills by autonomous fuzzy behavior control on an FPGA-based car-like mobile robot THS Li, SJ Chang, YX Chen. 2003. IEEE Transactions on Industrial …
- FPGA-based real-time power converter failure diagnosis for wind energy conversion systems S Karimi, A Gaillard, P Poure…. 2008. IEEE Transactions on …
- Maximum power point tracking using a GA optimized fuzzy logic controller and its FPGA implementation A Messai, A Mellit, A Guessoum, SA Kalogirou. 2011. Solar energy
- Closing the gap: CPU and FPGA trends in sustainable floating-point BLAS performance KD Underwood, KS Hemmert. 2004. 12th Annual IEEE Symposium …
- A 90nm low-power FPGA for battery-powered applications T Tuan, S Kao, A Rahman, S Das…. 2006. Proceedings of the 2006 …
- FPGA routing architecture: Segmentation and buffering to optimize speed and density V Betz, J Rose. 1999. Proceedings of the 1999 ACM/SIGDA seventh …
- Compiling pcre to fpga for accelerating snort ids A Mitra, W Najjar, L Bhuyan. 2007. Proceedings of the 3rd ACM/IEEE …
- Improved ring oscillator PUF: An FPGA-friendly secure primitive A Maiti, P Schaumont. 2011. Journal of cryptology
- Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics F Li, Y Lin, L He, J Cong, J Cong. 2004. Proceedings of the 2004 ACM/SIGDA …
- FPGA architecture with repeatable titles including routing matrices and logic matrices D Tavana, WK Yee, VA Holen. 1999. US Patent 5,883,525
- FPGA having logic element carry chains capable of generating wide XOR functions K Chaudhary. 1999. US Patent 5,889,411
- Design and implementation of modular FPGA-based PID controllers YF Chan, M Moallem, W Wang. 2007. IEEE transactions on Industrial …
- On the vulnerability of FPGA bitstream encryption against power analysis attacks: extracting keys from xilinx Virtex-II FPGAs A Moradi, A Barenghi, T Kasper, C Paar. 2011. … of the 18th ACM conference on …
- FPGA-based real-time emulation of power electronic systems with detailed representation of device characteristics A Myaing, V Dinavahi. 2010. IEEE transactions on Industrial …
- Built-in self-test of FPGA interconnect C Stroud, S Wijesuriya, C Hamilton…. 1998. … 1998 (IEEE Cat. No …
- Worm-hole run-time reconfigurable processor field programmable gate array (FPGA) P Athanas, RA Bittner Jr. 1998. US Patent 5,828,858
- MONTAGE: An FPGA for synchronous and asynchronous circuits S Hauck, G Borriello, S Burns, C Ebeling. 1992. International Workshop on Field …
- Leakage power analysis of a 90nm FPGA T Tuan, B Lai. 2003. Proceedings of the IEEE 2003 Custom …
- A synchronized visual-inertial sensor system with FPGA pre-processing for accurate real-time SLAM J Nikolic, J Rehder, M Burri, P Gohl…. 2014. … on robotics and …
- Universal switch modules for FPGA design YW Chang, DF Wong, CK Wong. 1996. ACM Transactions on Design …
- Feedforward neural network implementation in FPGA using layer multiplexing for effective resource utilization S Himavathi, D Anitha…. 2007. IEEE Transactions on …
- Fpga-accelerated simulation technologies (fast): Fast, full-system, cycle-accurate simulators D Chiou, D Sunwoo, J Kim, NA Patil…. 2007. 40th Annual IEEE …
- Power-analysis attacks on an FPGA–first experimental results SB Örs, E Oswald, B Preneel. 2003. International Workshop on Cryptographic …
- The design of a low energy FPGA V George, H Zhang, J Rabaey. 1999. … 1999 International Symposium …
- Improving FPGA design robustness with partial TMR B Pratt, M Caffrey, P Graham, K Morgan…. 2006. 2006 IEEE …
- A fixed-frequency quasi-sliding control algorithm: application to power inverters design by means of FPGA implementation RR Ramos, D Biel, E Fossas…. 2003. IEEE Transactions on …
- Rijndael FPGA implementations utilising look-up tables M McLoone, JV McCanny. 2003. Journal of VLSI signal processing systems for …
- FPGA-based controllers E Monmasson, L Idkhajine…. 2011. IEEE Industrial …
- Supporting multiple FPGA configuration modes using dedicated on-chip processor AH Lesea, SM Trimberger. 2002. US Patent 6,496,971
- Effects of FPGA architecture on FPGA routing S Trimberger. 1995. 32nd Design Automation Conference
- Cut Ranking and Pruning: Enabling A General And E cient FPGA Mapping Solution J Cong, C Wu, Y Ding. 1999. … 4th International Symposium on FPGA
- Fpga-based face detection system using haar classifiers J Cho, S Mirzaei, J Oberg, R Kastner. 2009. Proceedings of the ACM/SIGDA …
- Concurrent and simple digital controller of an AC/DC converter with power factor correction based on an FPGA A de Castro, P Zumel, O García…. 2003. IEEE Transactions on …
- BDD based decomposition of logic functions with application to FPGA synthesis YT Lai, M Pedram, SBK Vrudhula. 1993. 30th ACM/IEEE Design …
- High speed processing of financial information using FPGA devices S Parsons, DE Taylor, DV Schuehler…. 2011. US Patent …
- FPGA implementations of fast Fourier transforms for real-time signal and image processing IS Uzun, A Amira, A Bouridane. 2005. IEE Proceedings-Vision, Image and Signal …
- FPGA design automation: A survey D Chen, J Cong, P Pan. 2006. Foundations and Trends® in …
- An implementation of fuzzy logic controller on the reconfigurable FPGA system D Kim. 2000. IEEE Transactions on industrial Electronics
- Configurable multilayer CNN-UM emulator on FPGA Z Nagy, P Szolgay. 2003. IEEE Transactions on Circuits and Systems …
- The 10-ps wave union TDC: Improving FPGA TDC resolution beyond its cell delay J Wu, Z Shi. 2008. 2008 IEEE Nuclear Science Symposium …
- Analysis and enhancement of random number generator in FPGA based on oscillator rings K Wold, CH Tan. 2009. International Journal of Reconfigurable Computing
- Real-time stereo vision system using semi-global matching disparity estimation: Architecture and FPGA-implementation C Banz, S Hesselbarth, H Flatt…. 2010. 2010 International …
- FPGA routing and routability estimation via Boolean satisfiability RG Wood, RA Rutenbar. 1998. … on Very Large Scale Integration (VLSI …
- An FPGA run-time system for dynamical on-demand reconfiguration M Ullmann, M Hübner, B Grimm…. 2004. … Parallel and Distributed …
- Multitasking on FPGA coprocessors H Simmler, L Levinson, R Männer. 2000. International Workshop on Field …
- Blas comparison on fpga, cpu and gpu S Kestur, JD Davis, O Williams. 2010. 2010 IEEE computer society …
- Configuring an FPGA using embedded memory GR Lawman. 2000. US Patent 6,049,222
- Configuration compression for the Xilinx XC6200 FPGA S Hauck, Z Li, E Schwabe. 1998. Proceedings. IEEE Symposium on …
- A 54 mbps (3, 6)-regular FPGA LDPC decoder T Zhang, KK Parhi. 2002. IEEE workshop on signal processing …
- Effectiveness of internal versus external SEU scrubbing mitigation strategies in a Xilinx FPGA: Design, test, and analysis M Berg, C Poivey, D Petrick, D Espinosa…. 2008. … on Nuclear Science
- FPGA configuration circuit including bus-based CRC register DP Schultz, LC Hung, FE Goetting. 2001. US Patent 6,191,614
- FPGA switch block layout and evaluation H Schmit, V Chandra. 2002. Proceedings of the 2002 ACM/SIGDA tenth …
- DAOmap: A depth-optimal area optimization mapping algorithm for FPGA designs D Chen, J Cong. 2004. Proceedings of the 2004 IEEE/ACM International …
- RIFFA 2.1: A reusable integration framework for FPGA accelerators M Jacobsen, D Richmond, M Hogains…. 2015. ACM Transactions on …
- FPGA implementation of matrix inversion using QRD-RLS algorithm M Karkooti, JR Cavallaro, C Dick. 2005. Asilomar Conference on …
- FPGA lookup table with transmission gate structure for reliable low-voltage operation T Pi, PJ Crotty. 2003. US Patent 6,667,635
- DAG-Map: Graph-based FPGA technology mapping for delay optimization KC Chen, J Cong, Y Ding, AB Kahng…. 1992. IEEE Design & Test of …
- Advanced reliability study of TSV interposers and interconnects for the 28nm technology FPGA B Banijamali, S Ramalingam…. 2011. 2011 IEEE 61st …
- New performance-driven FPGA routing algorithms MJ Alexander, G Robins. 1996. IEEE Transactions on Computer …
- Hybrid FPGA architecture A Kaviani, S Brown. 1996. Fourth International ACM Symposium on …
- Interpolating time counter with 100 ps resolution on a single FPGA device R Szplet, J Kalisz…. 2000. IEEE Transactions on …
- FPGA implementation of embedded fuzzy controllers for robotic applications S Sánchez Solano, A Cabrera…. 2007. IEEE Transactions on …
- Realtime ray tracing of dynamic scenes on an FPGA chip J Schmittler, S Woop, D Wagner, WJ Paul…. 2004. Proceedings of the …
- A time-multiplexed FPGA architecture for logic emulation D Jones, DM Lewis. 1995. Proceedings of the IEEE 1995 Custom …
- Low-energy embedded FPGA structures E Kusse, J Rabaey. 1998. … on Low Power Electronics and Design …
- Fast elliptic curve cryptography on FPGA WN Chelton, M Benaissa. 2008. … on very large scale integration (VLSI …
- Dynamic and partial FPGA exploitation J Becker, M Hubner, G Hettich…. 2007. Proceedings of the …
- FPMR: MapReduce framework on FPGA Y Shan, B Wang, J Yan, Y Wang, N Xu…. 2010. Proceedings of the 18th …
- Achieving high performance with FPGA-based computing MC Herbordt, T VanCourt, Y Gu, B Sukhwani…. 2007. Computer
- On the interaction between power-aware FPGA CAD algorithms J Lamoureux, SJE Wilton. 2003. Proceedings of the 2003 IEEE/ACM …
- Exploring area/delay tradeoffs in an AES FPGA implementation J Zambreno, D Nguyen, A Choudhary. 2004. International Conference on Field …
- Programming models for hybrid FPGA-CPU computational components: a missing link D Andrews, D Niehaus, R Jidin, M Finley, W Peck…. 2004. IEEE micro
- A comparative study of two Boolean formulations of FPGA detailed routing constraints GJ Nam, F Aloul, KA Sakallah…. 2004. IEEE Transactions on …
- A new duty cycle control strategy for power factor correction and FPGA implementation W Zhang, YF Liu, B Wu. 2006. IEEE transactions on power …
- A C++ compiler for FPGA custom execution units synthesis C Iseli, E Sanchez. 1995. … IEEE Symposium on FPGAs for Custom …
- FPGA implementation of MD5 hash algorithm J Deepakumara, HM Heys…. 2001. … Conference on Electrical …
- An FPGA for implementing asynchronous circuits S Hauck, S Burns, G Borriello…. 1994. IEEE Design & Test of …
- An asynchronous dataflow FPGA architecture J Teifel, R Manohar. 2004. IEEE Transactions on Computers
- World's first monolithic 3D-FPGA with TFT SRAM over 90nm 9 layer Cu CMOS T Naito, T Ishida, T Onoduka…. 2010. 2010 Symposium on …
- Exploring potential benefits of 3D FPGA integration C Ababei, P Maidee, K Bazargan. 2004. International Conference on Field …
- An automated temporal partitioning and loop fission approach for FPGA based reconfigurable synthesis of DSP applications M Kaul, R Vemuri, S Govindarajan…. 1999. … Conference (Cat. No …
- An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs J Cong, Y Ding. 2003. The Best of ICCAD
- Method and apparatus for incorporating a multiplier into an FPGA BJ New, SP Young. 2002. US Patent 6,362,650
- NoC-based FPGA: architecture and routing R Gindin, I Cidon, I Keidar. 2007. … on Networks-on-Chip (NOCS'07)
- 160-fold acceleration of the Smith-Waterman algorithm using a field programmable gate array (FPGA) ITS Li, W Shum, K Truong. 2007. BMC bioinformatics
- An FPGA-based performance analysis of the unrolling, tiling, and pipelining of the AES algorithm GP Saggese, A Mazzeo, N Mazzocca…. 2003. … Conference on Field …
- Interconnect pipelining in a throughput-intensive FPGA architecture A Singh, A Mukherjee, M Marek-Sadowska. 2001. Proceedings of the 2001 …
- FPGA implementation of the power electronic converter model for real-time simulation of electromagnetic transients M Matar, R Iravani. 2009. IEEE Transactions on Power Delivery
- FPGA-based stochastic neural networks-implementation SL Bade, BL Hutchings. 1994. … of IEEE Workshop on FPGA's for …
- FPGA implementation of digital filters CJ Chou, S Mohanakrishnan, JB Evans. 1993. Proc. Icspat
- BIST-based test and diagnosis of FPGA logic blocks M Abramovici, CE Stroud. 2001. IEEE Transactions on Very Large …
- FPGA vendor agnostic true random number generator D Schellekens, B Preneel…. 2006. … Conference on Field …
- Comparison of the FPGA implementation of two multilevel space vector PWM algorithms Ó López, J Alvarez, J Doval-Gandoy…. 2008. IEEE Transactions …
- Development of an FPGA-based system for real-time simulation of photovoltaic modules E Koutroulis, K Kalaitzakis, V Tzitzilonis. 2009. Microelectronics journal
- Spin transfer torque (STT)-MRAM--based runtime reconfiguration FPGA circuit W Zhao, E Belhaire, C Chappert…. 2009. ACM Transactions on …
- The SFRA: a corner-turn FPGA architecture N Weaver, J Hauser, J Wawrzynek. 2004. … of the 2004 ACM/SIGDA 12th …
- Evaluation of the streams-C C-to-FPGA compiler: an applications perspective J Frigo, M Gokhale, D Lavenier. 2001. Proceedings of the 2001 ACM/SIGDA …
- FPGA PUF using programmable delay lines M Majzoobi, F Koushanfar…. 2010. 2010 IEEE International …
- A fault injection analysis of Virtex FPGA TMR design methodology F Lima, C Carmichael, J Fabula…. 2001. … 2001. 2001 6th …
- A novel predictable segmented FPGA routing architecture ES Ochotta, PJ Crotty, CR Erickson, CT Huang…. 1998. Proceedings of the …
- Test of RAM-based FPGA: Methodology and application to the interconnect M Renovell, J Figueras, Y Zorian. 1997. Proceedings. 15th IEEE …
- Packet switched vs. time multiplexed FPGA overlay networks N Kapre, N Mehta, M Delorimier…. 2006. 2006 14th Annual …
- Fully integrated FPGA-based controller for synchronous motor drive L Idkhajine, E Monmasson, MW Naouar…. 2009. IEEE Transactions …
- Radiation test results of the Virtex FPGA and ZBT SRAM for space based reconfigurable computing E Fuller, M Caffrey, P Blain…. 1999. MAPLD …
- Optimal FPGA module placement with temporal precedence constraints S Fekete, E Kohler, J Teich. 2001. Proceedings Design, Automation …
- Iterative and adaptive slack allocation for performance-driven layout and FPGA routing J Frankle. 1992. [1992] Proceedings 29th ACM/IEEE Design …
- Automatic allocation of arrays to memories in FPGA processors with multiple memory banks MB Gokhale, JM Stone. 1999. Seventh Annual IEEE Symposium on …
- Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration M Huebner, T Becker, J Becker. 2004. Proceedings of the 17th symposium on …
- PNoC: a flexible circuit-switched NoC for FPGA-based systems C Hilton, B Nelson. 2006. IEE Proceedings-Computers and Digital Techniques
- Power Analysis of an FPGA FX Standaert, SB Örs, B Preneel. 2004. International Workshop on …
- FPGA Programming for the Masses. DF Bacon, RM Rabbah, S Shukla. 2013. Commun. ACM
- Autonomous fault emulation: A new FPGA-based acceleration system for hardness evaluation C Lopez-Ongil, M Garcia-Valderas…. 2007. … on Nuclear Science
- Design and implementation of a high level programming environment for FPGA-based image processing D Crookes, K Benkrid, A Bouridane, K Alotaibi…. 2000. IEE Proceedings-Vision …
- A FPGA implementation of model predictive control KV Ling, SP Yue, JM Maciejowski. 2006. 2006 American Control …
- FPGA power reduction using configurable dual-Vdd F Li, Y Lin, L He. 2004. Proceedings of the 41st annual design automation …
- An innovative, segmented high performance FPGA family with variable-grain-architecture and wide-gating functions O Agrawal, H Chang, B Sharpe-Geisler…. 1999. Proceedings of the …
- FPGA partial reconfiguration via configuration scrubbing J Heiner, B Sellers, M Wirthlin…. 2009. … Conference on Field …
- BIST-based diagnostics of FPGA logic blocks C Stroud, E Lee, M Abramovici. 1997. Proceedings International Test …
- A study of the speedups and competitiveness of FPGA soft processor cores using dynamic hardware/software partitioning R Lysecky, F Vahid. 2005. Design, Automation and Test in Europe
- FPGA design by generalized functional decomposition T Sasao. 1993. Logic synthesis and optimization
- mrFPGA: A novel FPGA architecture with memristor-based reconfiguration J Cong, B Xiao. 2011. 2011 IEEE/ACM international symposium on …
- An efficient FPGA implementation of advanced encryption standard algorithm SS Wang, WS Ni. 2004. … Symposium on Circuits and Systems (IEEE …
- FPGA adders: Performance evaluation and optimal design S Xing, WWH Yu. 1998. IEEE Design & Test of Computers
- Maxwell-a 64 FPGA supercomputer R Baxter, S Booth, M Bull, G Cawood…. 2007. Second NASA/ESA …
- Scheduling designs into a time-multiplexed FPGA S Trimberger. 1998. Proceedings of the 1998 ACM/SIGDA sixth …
- Consequences and categories of SRAM FPGA configuration SEUs P Graham, M Caffrey, J Zimmerman…. 2003. In Proceedings of the …
- Compact FPGA-based true and pseudo random number generators KH Tsoi, KH Leung, PHW Leong. 2003. 11th Annual IEEE …
- RAMP gold: an FPGA-based architecture simulator for multiprocessors Z Tan, A Waterman, R Avizienis, Y Lee…. 2010. Proceedings of the 47th …
- … approach to the decomposition of incompletely specified multi-output functions based on graph coloring and local transformations and its application to FPGA … W Wan, MA Perkowski. 1992. Proceedings of the conference on European …
- Design and implementation of an FPGA-based control IC for AC-voltage regulation SL Jung, MY Chang, JY Jyang…. 1999. IEEE Transactions on …
- How much logic should go in an FPGA logic block V Betz, J Rose. 1998. IEEE Design & Test of Computers
- The reliability of FPGA circuit designs in the presence of radiation induced configuration upsets M Wirthlin, E Johnson, N Rollins…. 2003. 11th Annual IEEE …
- SRAM based re-programmable FPGA for space applications JJ Wang, RB Katz, JS Sun, BE Cronquist…. 1999. … on Nuclear Science
- A Dual-VDD Low Power FPGA Architecture A Gayasen, K Lee, N Vijaykrishnan…. 2004. … Conference on Field …
- Low-power high-level synthesis for FPGA architectures D Chen, J Cong, Y Fan. 2003. … of the 2003 international symposium on Low …
- Artificial neural network implementation on a single FPGA of a pipelined on-line backpropagation R Gadea, J Cerdá, F Ballester, A Mocholí. 2000. Proceedings of the 13th …
- An analysis of delay based PUF implementations on FPGA S Morozov, A Maiti, P Schaumont. 2010. International Symposium on Applied …
- An assessment of the suitability of FPGA-based systems for use in digital signal processing RJ Petersen, BL Hutchings. 1995. … Workshop on Field Programmable Logic and …
- An efficient algorithm for finding empty space for online FPGA placement M Handa, R Vemuri. 2004. Proceedings of the 41st annual Design …
- FPGA Verification of a Single QC-LDPC Code for 100 Gb/s Optical Systems without Error Floor down to BER of 10-15 D Chang, F Yu, Z Xiao, Y Li, N Stojanovic…. 2011. Optical Fiber …
- Xilinx stacked silicon interconnect technology delivers breakthrough FPGA capacity, bandwidth, and power efficiency K Saban. 2011. Xilinx, White Paper
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